1. Field of the Invention
The present invention relates to a phase lock loop circuit, and more particularly to a phase lock loop circuit suitable for constituting a frequency synthesizer capable of obtaining an output frequency having a higher frequency resolution than a reference frequency by utilizing a fractional division.
2. Description of the Related Art
FIG. 8 is a block diagram showing a conventional phase lock (PLL) loop circuit.
As shown in FIG. 8, the phase look loop circuit has such a structure that an output of a voltage control oscillator 27 is divided by a variable divider 21, and the output thus divided is phase compared with a reference signal 25 in a phase comparator 24 and is connected to a frequency control input 34 of the voltage control oscillator 27 through an LPF 26.
A fractional division produces the following equation by using some variable divisions:
Average division number=N+L/A. 
In a division switching calculating circuit 31, a division value to be set next is calculated through a variable divider output 29. After the calculation, the variable divider 21 is controlled through a division switching control circuit 22.
In the case of such fractional division control, for example, a xcexa3xcex94 (sigma delta) modulator is used as a modulating method of increasing a band of a noise generated through division value switching of a divider (noise shaping) in accordance with a calculation algorithm.
As a specific example of the xcexa3xcex94 (sigma delta) modulator, a tertiary MASH type xcexa3xcex94 (sigma delta) modulator shown in FIG. 7 has been described in xe2x80x9cOversampling A-D Converting Techniquexe2x80x9d written by Akira Yukawa, Nikkei BP Co., Ltd. Moreover, JP-A-4-212522 has disclosed an example in which the xcexa3xcex94 (sigma delta) modulator is used for a PLL synthesizer.
In the conventional phase lock loop circuit, however, every time the variable divider output 29 is generated, a next fractional division value is calculated through an operation circuit (hardware) or a software operation in accordance with an algorithm. Therefore, a constant time is required for the calculation. In the algorithm, a dependent connection type is used as in the MASH type xcexa3xcex94 (sigma delta) modulation. Therefore, a long time is required for the operation. Moreover, the operation circuit (hardware) for the calculation is also complicated.
In such a circuit structure, moreover, a constant time is required for divider switching and a reference frequency is reduced.
Furthermore, there is also a problem in that the phase lock loop has a small noise suppression frequency width and a long time required for frequency switching.
The invention has been made in consideration of the problems and has an object to implement a phase lock loop circuit capable of realizing a fractional dividing circuit with a simple circuit, carrying out divider switching at a high speed, setting a reference frequency to be high, and furthermore, setting a noise suppression frequency width to be great through a phase lock loop and also shortening a time required for frequency switching.
In order to achieve the object, according to a first aspect of the invention, there is provided a phase lock loop circuit for switching a division ratio of a variable divider, thereby carrying out a fractional division, comprising a variable divider capable of varying a division ratio of an output of a voltage control oscillator in response to a divider control signal, operation means for previously calculating divider control data for obtaining a division number corresponding to an output frequency, a divider switching memory circuit for writing the divider control data and reading the data every time an output of the variable divider is generated, thereby setting a division value of the variable divider, a phase comparator for phase comparing the output of the variable divider with a reference frequency, an LPF (low-pass filter) for inputting an output of the phase comparator and removing a high frequency component, and the voltage control oscillator capable of changing an oscillation frequency through an output of the LPF (low-pass filter).
Moreover, according to a second aspect of the invention, there is provided the phase lock loop circuit according to the first aspect wherein the variable divider can switch a division ratio, thereby obtaining an average division number (N+L/A) (N, L and A are integers)
Furthermore, according to a third aspect of the invention, there is provided the phase lock loop circuit according to the first or second aspect wherein the operation means previously calculates a division value in accordance with a calculation algorithm through xcexa3xcex94 (sigma delta) modulation.
Moreover, according to a fourth aspect of the invention, there is provided the phase lock loop circuit according to any one of the first to third aspects wherein the divider switching memory circuit writes the divider control data to a memory, counts divider outputs through a counter to set a read address of the memory, and transmits read data to the variable divider, thereby setting a division value.
Furthermore, according to a fifth aspect of the invention, there is provided the phase lock loop circuit according to any one of the first to third aspects wherein the memory includes a plurality of memory blocks, writes the divider control data having different frequencies to the different memory blocks for the respective frequencies and switches the memory blocks for reading, thereby changing over the frequencies.